Minimizing Processor Power Dissipation with Self-tuning Techniques

Abstract

Today, safety margins are causing significant amount of unnecessary power overhead or limiting the performance of the conventional digital designs. In order to minimize the overhead of safety margins, there is an increasing interest for adaptive techniques. One of the first and well known adaptive technique which minimizes the overhead of entire safety margins is dubbed Razor [1]. This thesis work is a case study of implementation and evaluation of the Razor approach on a processor which executes a subset of the AVR32 instruction set. ATMEL 150nm low leakage library is used for synthesize and evaluations. A methodology is explained to introduce the Razor approach to the pipeline with one-cycle error recovery. Simulations showed that at least 26-28% reduction in energy is possible on typical library conditions over the supply voltage determined by the worst case safety margins.