Implementing stereoscopic video processing on FPGA

dc.contributor.author	Hjartarson, Ástvaldur
dc.contributor.author	Nordmark, Klas
dc.contributor.department	Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)	sv
dc.contributor.department	Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)	en
dc.date.accessioned	2019-07-03T13:43:59Z
dc.date.available	2019-07-03T13:43:59Z
dc.date.issued	2015
dc.description.abstract	The purpose of this thesis is to investigate the viability of using FPGA acceleration in the processing of a stereoscopic video feed. This is done by comparing speed for a given processing resolution with a software implementation, as well as investigating power and area usage. The processing performed include greyscaling, remapping, resizing, Gaussian blur and Sobel filtering. Methods for disparity map calculations are also investigated. A system capable of processing video at 60 stereo frame pairs per second was developed.
dc.identifier.uri	https://hdl.handle.net/20.500.12380/219423
dc.language.iso	eng
dc.setspec.uppsok	Technology
dc.subject	Informations- och kommunikationsteknik
dc.subject	Data- och informationsvetenskap
dc.subject	Information & Communication Technology
dc.subject	Computer and Information Science
dc.title	Implementing stereoscopic video processing on FPGA
dc.type.degree	Examensarbete för masterexamen	sv
dc.type.degree	Master Thesis	en
dc.type.uppsok	H
local.programme	Embedded electronic system design (MPEES), MSc

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