High-throughput Low-power BCH Decoder for Short-reach Optical Communication System

Abstract

Short-reach optical systems in data centers or high-performance computing systems are often subjected to harsh environmental conditions, especially high temperatures. These elevated temperatures can lead to various challenges, including high bit-error rates (BER) and lower data rates. In order to mitigate those problems, forward error corrections (FEC) can be employed. A suitable FEC can also help to reduce the total system power by relaxing the optical modulation amplitude (OMA) requirement at the receiver. FEC consists of two functional blocks, an encoder and a decoder. Compared with the encoder, the decoder significantly influences area usage and power consumption of the FEC. Among FEC alternatives, Bose–Chaudhuri–Hocquenghem (BCH) is favorable regarding the hardware complexity and error correction ability. In this work, we propose a BCH decoder circuit with error correction ability t = 3 and 4, and implement its corresponding encoder in order to evaluate the overall system power-dissipation reduction. We also propose an estimation model based on MATLAB to predict the performance of different system architectures and key equation solving algorithms. Based on the estimation result, a reformulated inversionless Berlekamp-Massey (riBM) algorithm is selected for the key equation solver and the unrolled pipeline (UP) system architecture is implemented to increase the throughput and reduce the power consumption. A system based on iterative parallel (IP) architecture is also implemented as a comparison architecture. Compared with the IP system, the UP system can save up to 20% power at an input BER of 10−3 in a 22-nm CMOS process technology. Including the power consumption of encoders and actual-case transmitters, the BCH FEC can significantly reduce the power by a maximum of 58% compared with the uncoded system in a 190-mW transmitter system.