JESD204 Receiver and Data Reduction Implementation for an SoC Platform

Abstract

Field programmable gate arrays (FPGAs) are currently used within the signal processing chain of space systems to transfer data from high-speed sensors. Such systems employ a number of FPGAs, that are primarily used for tasks such as data reception and data reduction, which is a critical step as microprocessors often struggle to handle data at such high rates. The FPGAs cause an overall increase in resource and power usage for the critical space computer systems with limited resources. This thesis presents a prototype implementation of a JESD204B high-speed serial receiver, together with an investigation of some existing data reduction algorithms that are suitable for hardware implementation.

The methodology used in this project involved constructing an SoC subsystem on an FPGA to create the signal processing chain needed to obtain high-speed communication. Formal verification methods were used extensively to verify the functionality of the receiver. Python was used to explore two different implementations for data reduction. The receiver RTL demonstrated correct behavioral functionality against a transmitter in simulation. Although the receiver was successfully implemented on the FPGA, actual data reception on the hardware was not achieved due to time limitations. The study of the algorithms showed valuable results, making them practical both for research and in terms of hardware implementation. Future work includes establishing receiver and transmitter communication to read actual data on hardware, further developing the receiver, and finally implementing the data reduction algorithms in hardware.