Design of a Down Converter for a Galileo Receiver

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dc.contributor.authorVickberg, Alexander
dc.contributor.authorWu, Yue
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T12:22:42Z
dc.date.available2019-07-03T12:22:42Z
dc.date.issued2010
dc.description.abstractThis report presents the work performed in the master thesis work "Design of a Down Converter for a Galileo Receiver". The thesis work has designed a receiver front-end down converter for the new European navigation system, Galileo. For this thesis work, the development platform Neptune-V5 VXS from Tekmicro has been used, which offers a highspeed RF sampling analogue-to-digital converter together with high-speed Xilinx Virtex-5 FPGAs. A digital down converter architecture utilizing direct RF sampling techniques is defined in this thesis work. The work also includes modeling the FPGA design in MATLAB, implementing this design in an FPGA using VHDL and targeting an ASIC implementation considering size/power constraints. Finally, through laboratory tests supported by analysis and/or system modeling the performance of key parameters have been tested.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/124116
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectDatorteknik
dc.subjectComputer Engineering
dc.titleDesign of a Down Converter for a Galileo Receiver
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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