Enhancing NOEL3 RISC-V processor with CHERI memory protection

Abstract

Memory safety vulnerabilities are a concern in modern computing systems. CHERI (Capability Hardware Enhanced RISC Instructions) is an architectural extension that replaces traditional pointers with capabilities that include permissions and bounds, among other metadata. This allows fine-grained memory protection and compartmentalization that provide guarantees against a number of these safety issues. This thesis presents the addition of CHERI into NOEL3, a 32-bit RISC-V processor characterized by its deterministic barrel architecture, multiple extensions and emphasis on fault tolerance and reliability. The baseline processor has been extended with the microarchitectural structures needed to support CHERI, such as capability registers, tags and enforcement logic. The implementation, targeting the KCU105 FPGA evaluation board, was verified and debugged by means of specific instruction tests through comparison with a golden signature to ensure compliance with the CHERI specification. With respect to the standard NOEL3 with Physical Memory Protection, results indicate an average clock rate degradation of 37 %, while resource utilization (heavily influenced by CLB LUTs) is increased by 38 %.