Test Vector Extraction Methodology For Power Integrity Analysis

Abstract

In order to decrease performance pessimism due to supply voltage uncertainties in integrated circuits, detailed power integrity analysis is necessary. Knowing the worstcase voltage drop that the circuit will encounter is a step towards this goal. The voltage drop is input-dependent, which means the outcome depends on how the chip is used. In this thesis, methods to extract the worst-case clock cycle out of a microprocessor run-trace are developed. The methods considered are based on time-based power simulations, considering full-chip total power in several time-resolutions, frequency based approaches using FFT and wavelets, and the spatial locality of switching activity. SPICE voltage drop simulations are performed while considering R and L components of the power grid, as well as decoupling capacitance and the gate switching extracted from the run-trace. Results show that the voltage drops found when focusing on spatial locality exceed the previous worst-case for the chip design by a factor of 2. This method considers the worst-case power grid node, finding the time-instance where maximum power dissipation of its adjacent nodes coincides with the maximum power dissipation of the chip’s CPU core. Attempts at alleviating these sparse and localized large voltage drops are performed through the use of skew-spreading. This method is shown to decrease the largest voltage drop found by over 20%.