Clock Synchronisation Method Over Bandwidth-Limited CAN-Bus
| dc.contributor.author | Mathiesen, Christoffer | |
| dc.contributor.author | Kvist, David | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data och informationsteknik | sv |
| dc.contributor.examiner | Larsson-Edefors, Per | |
| dc.contributor.supervisor | Svensson, Lars | |
| dc.date.accessioned | 2021-10-04T08:32:57Z | |
| dc.date.available | 2021-10-04T08:32:57Z | |
| dc.date.issued | 2021 | sv |
| dc.date.submitted | 2020 | |
| dc.description.abstract | Clock synchronisation is an integral part of systems where the ordering of events is needed. While implementations exist on the CAN-bus to provide clock synchronisa tion, additional improvements are needed to provide a robust protocol while limiting the amount of traffic used in a system. Many solutions rely on the entire system architecture to be known or a timekeeper be preassigned before the start of the sys tem, thus limiting the adaptability and/or scalability of the protocol. Here we aim to implement a solution that does not depend on knowledge of the number of nodes, and where each node can independently or collectively retain timekeeping regardless of what happens to the timekeeping master device. The timekeeping master node should not be necessary to be preassigned, instead, the system should be capable of arbitrating the master node at startup and achieve synchronicity. Furthermore, nodes should be able to arrive and leave an active system at any moment, also known as being hot-plug enabled. The nodes are envisioned to be of limited com putational ability and not necessarily be constructed with the same hardware. As such a protocol capable of handling counter rollover and devices with different local oscillator frequencies is to be designed. While a lot of design insight was gained and a demonstrator system was partially implemented in hardware the task was underestimated and ultimately not completed. A complete HDL-implementation might be very possible, but it might not be better than a system comprised of both hardware and software. | sv |
| dc.identifier.coursecode | DATX05 | sv |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/304216 | |
| dc.language.iso | eng | sv |
| dc.setspec.uppsok | Technology | |
| dc.subject | Timekeeping Synchronisation | sv |
| dc.subject | CAN | sv |
| dc.subject | FPGA | sv |
| dc.subject | Master-arbitration | sv |
| dc.title | Clock Synchronisation Method Over Bandwidth-Limited CAN-Bus | sv |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.uppsok | H | |
| local.programme | Embedded electronic system design (MPEES), MSc |