DESIGN AND FPGA PROTOTYPING OF A SEQUENCER IP CORE FOR GRLIB LIBRARY
| dc.contributor.author | LINGARDO, LUCA | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers) | sv |
| dc.contributor.department | Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers) | en |
| dc.date.accessioned | 2019-07-03T14:43:15Z | |
| dc.date.available | 2019-07-03T14:43:15Z | |
| dc.date.issued | 2018 | |
| dc.description.abstract | The following thesis work is aimed to describe the development of a sequencer IP core for GRLIB library, which fills a gap in the Cobham Gaisler’s IP portfolio. The faced problem was that some SoC systems cannot include a processor. The project proposed by Cobham Gailser AB aimed to develop a dedicated core able to write to memory-mapped registers. The developed sequencer IP core is aimed to replace the LEON processor in any LEON/GRLIB SoC design that cannot include it. It can configure the system both at power-on and dynamically at run time, as well as initializing the system memory by writing words of fixed value zero within its entries. The sequencer core can be programmed to: either configure the system at poweron only or both at power-on and run-time; either initialize the system memory or not; either react to synchronous or asynchronous reset signal. Its states-transition diagram is realized in such a way to maximize hardware re-usage. Moreover, the dimension of some of the internal blocks within the core is dictated through VHDL generics. This avoids to instantiate useless hardware resources with respect to the real need. The correct functioning of the developed sequencer IP core is demonstrated by showing some valuable simulation results. The final goal of the project was also fulfilled, namely to develop a sequencer IP core far smaller than a LEON3 processor. Indeed, the developed sequencer results to use around seven times less hardware resources than the LEON3 processor. Moreover, the sequencer shows a gap equal to the 0.50% of additional hardware resources between the smallest and the biggest configuration among those available. The implemented burst mode for memory initialization also showed huge advantages in terms of time required to execute such operation. Indeed, the sequencer resulted to be eight times faster by using burst mode to initialize a memory of 1024 entries in simulation than without using it. | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/255059 | |
| dc.language.iso | eng | |
| dc.setspec.uppsok | Technology | |
| dc.subject | Data- och informationsvetenskap | |
| dc.subject | Informations- och kommunikationsteknik | |
| dc.subject | Computer and Information Science | |
| dc.subject | Information & Communication Technology | |
| dc.title | DESIGN AND FPGA PROTOTYPING OF A SEQUENCER IP CORE FOR GRLIB LIBRARY | |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.degree | Master Thesis | en |
| dc.type.uppsok | H | |
| local.programme | Embedded electronic system design (MPEES), MSc |