Instruction Decoder design for the FlexCore Processor

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dc.contributor.authorBUZDAR, ABDUL REHMAN
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T12:32:32Z
dc.date.available2019-07-03T12:32:32Z
dc.date.issued2010
dc.description.abstractThe goal of this project is to design an instruction decoder for the FlexCore processor based on an instruction compression scheme that would be used in implementing the instruction decoder circuitry. The instruction decoder is implemented using VHDL and an optimal compression scheme considering the FlexCore processor requirements. Later the VHDL description of the instruction decoder was synthesized using Cadence RTL compiler to study the impact of instruction decoder on the FlexCore processor performance in terms of timing, area and power requirements. The report also gives an analysis of various parameters of the compression scheme that would have an impact on the overall performance of the instruction decoder and eventually the FlexCore.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/137820
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectInformations- och kommunikationsteknik
dc.subjectGrundläggande vetenskaper
dc.subjectInnovation och entreprenörskap (nyttiggörande)
dc.subjectDatorteknik
dc.subjectInformation & Communication Technology
dc.subjectBasic Sciences
dc.subjectInnovation & Entrepreneurship
dc.subjectComputer Engineering
dc.titleInstruction Decoder design for the FlexCore Processor
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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