Power Integrity Analysis of AVR Processor

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dc.contributor.authorRavi, Badri Narayanan
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T12:28:46Z
dc.date.available2019-07-03T12:28:46Z
dc.date.issued2010
dc.description.abstractIn the deep submicron era, the power supply voltage to the logic devices should be well within the bound limits. The degradation of power affects the timing closure of the chip, thus affecting the performance. In this thesis, the analysis flow used in previous study is modified to make it generic to all series of AVR processors. By extracting a power grid model and subjecting it to extensive simulations, the issue causing the power degradation is analysed. Analysis results show that the cause for the first voltage drop is due to two factors, that is, current loads and resistive property of the metal wires. The first overshoot after voltage drop increases for wider metal wires compared to lesser width of metal wires. Nodes of the power grid having large voltage drop show that on-chip self inductance can no longer be ignored in designing power distribution networks for high frequency circuits.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/131944
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectDatorteknik
dc.subjectComputer Engineering
dc.titlePower Integrity Analysis of AVR Processor
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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