Baseband Inter-Chip Communication Interface Simulation for Baseband ASIC Multi-Processor Chip

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dc.contributor.authorAndersson, Robin
dc.contributor.authorJacobsson, Niclas
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T13:02:06Z
dc.date.available2019-07-03T13:02:06Z
dc.date.issued2012
dc.description.abstractIn this thesis simulations of a baseband inter-chip communication interface are implemented in CoFluent Studio. This was done to investigate whether CoFluent Studio could be used to aid development process of baseband chips and also improve performance of these systems by using these models. The software models of the system included four Application Specific Integrated Circuits (ASIC) connected by a network consisting of four switches, where each individual model implements a specific scheduling discipline. Comparison between scheduling disciplines was performed. These consisted of strict priority (SP), round robin (RR), time-division multiplexing (TMD) and asynchronous latency guarantee (ALG) scheduling. Another addition to tested scheduling principles was a modification of ALG that was created by the authors which allowed for configuring bandwidth between priorities. This scheduling discipline was called Configurable Asynchronous Latency Guarantee(CALG). The simulations were conducted using stimuli-data consisting of four different priorities which represents a typical traffic scenario within such baseband chip. The traffic data is transmitted over a Transmission Time Interval (TTI) of 2 ms where the highest priority data, representing time critical data, was sent as bursts while lower priorities were distributed uniformly over the remaining interval. The results of RR and TDM showed that their properties yielded high priority latencies of 54.7 and 91.7 s respectively. ALG resulted in 53.4 high priority latency and 19.4, 19.5 and 19.7 s for the respective BE data. The default SP scheduling yielded results in which high priority data had a Guaranteed Latency (GL) of 19.2 s while lower priorities made Best Effort (BE) latencies of 118.4, 126.7 and 139.3 s respectively. By using CALG the GL was relaxed to a limit of 25 s, which gave rise to lower BE latencies of 100.1, 104.1 and 98.1 s for the lower priorities. The results yielded from the CALG shows an latency improvement for low priority data of 18.3, 22.6 and 41.2 s respectively, while maintaining a GL of 25 s for high priority data. The original ALG has a 178.1% higher GL compared to the default SP scheduling. The configurable parameter of CALG showed that by relaxing GL to 25 s its latency became 29.6% higher than the GL of default SP scheduling. This shows that the CALG is more suitable than ALG for bursty data traffic.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/165541
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectData- och informationsvetenskap
dc.subjectComputer and Information Science
dc.titleBaseband Inter-Chip Communication Interface Simulation for Baseband ASIC Multi-Processor Chip
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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