An HDL-parameterizable m x n systolicarray- based matrixmultiplier for DNN applications

Abstract

Deep Neural Networks (DNNs) and its applications have been employed in different platforms with different requirements and resource constrains. General Matrix Multiplication (GEMM) is a common way to compute convolution which represents the most computationally demanding operation in DNNs. The variation in convolutional layers’ shapes and sizes results in different GEMM parameters. In this work, two versions of a matrix multiplier are presented. Both accelerators are designed using VHDL-93, are parameterizable at the Hardware Description Language (HDL) level and capable of multiplying m x n matrices using non-squared Systolic Arrays (SAs). v1 is capable of multiplying matrices of the size and shape of the SA and leave multiplying larger matrices as software overhead by re-feeding tiles of the same size to the accelerator. v2 on the other hand is capable of multiplying matrices that are larger than the used SA improving performance by on-chip feedback. On the other hand, resource utilization, specifically BRAM utilization in v1 is less than that in v2 giving the same SA shape since there is no need to save all tiles’ parameters before the start of the execution. Thus available resources (higher DSP/MAC resources in v1 and higher BRAM in v2) make a specific version preferable to another to achieve the same acceleration.