Design and Implementation of an AMBA CHI-Compliant Snoop Cache Coherence Controller

Abstract

In a multi-processor system, efficient cache coherence mechanisms are important for ensuring that data in every cache remains up-to-date across different cores. The AMBA Coherent Hub Interface (CHI) is a high-performance, scalable protocol designed by ARM to address the challenges of modern system-on-chip (SoC) architectures. This thesis presents the design and implementation of a snoop cache coherence controller using the AMBA CHI protocol. The snoop cache coherence controller is not only to ensure data consistency among the processors but also to reduce the network traffic through the snoop filter in the controller. In this thesis, we designed and implemented a cache coherence controller in hardware description language (HDL), and we used a multi-processor simulator named Multi- CacheSim and SPLASH-3 benchmark to model and test two kinds of snoop filters, counting stream register and cache-like snoop filter, and evaluate their message filter rate which represents the performance in snoop traffic reduction. The results demonstrate that the snoop-based CHI-compliant coherence controller can effectively maintain cache coherence in a multi-processor system based on CHI architecture. Additionally, the cache-like snoop filter can reduce network traffic. By comparing the results of the snoop filters, we can conclude that in most cases, the cache-like snoop filter performs better than the snoop filter based on a stream register. However, both have their advantages, with each performing better under certain circumstances.