Design of a phase locked loop for 60 GHz/ 30 GHz signal generation in 22nm FDSOI technology for wireless transceivers

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dc.contributor.authorBhuvanendran Sathiabhama, Sajeendran
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T14:59:55Z
dc.date.available2019-07-03T14:59:55Z
dc.date.issued2019
dc.description.abstractPhase Locked Loops (PLLs) are fundamental components in communication systems used in frequency synthesis, carrier recovery and modulation. Massive Multiple Input Multiple Output (MIMO) based millimeter wave communication systems demand reference frequencies with high spectral purity. Low power implementation of PLLs in deep submicron CMOS processes is essential in the current market demand for integrated transceivers for future communication systems like 5G. This thesis deals with the design of a 60 GHz PLL in 22nm FDSOI technology for use in 5G transceiver systems.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/256662
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectInformations- och kommunikationsteknik
dc.subjectData- och informationsvetenskap
dc.subjectInformation & Communication Technology
dc.subjectComputer and Information Science
dc.titleDesign of a phase locked loop for 60 GHz/ 30 GHz signal generation in 22nm FDSOI technology for wireless transceivers
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
local.programmeEmbedded electronic system design (MPEES), MSc
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