Comparative performance analysis of high-level synthesis and RTL implementations of LDPC decoders

Abstract

Low density parity check codes are an important type of error-correcting codes used in many modern communications standards. Implementing LDPC decoders efficiently in hardware is a key requirement, as these systems demand both high throughput and low latency. This thesis compares two design approaches for LDPC decoder implementation: the conventional Register Transfer Level (RTL) method and High-Level Synthesis (HLS). The RTL design provides detailed control over timing and hardware resources but requires significant development effort. HLS, on the other hand, allows designers to describe the algorithm in C/C++ and semiautomatically generate RTL, reducing design time and offering faster exploration of architectural trade-offs. In this work, both RTL and HLS implementations of an LDPC decoder were developed and evaluated. Metrics such as latency, setup and hold times, maximum operating frequency, and resource utilization were compared.