On-Chip Diplexer Design for Travelling Wave Parametric Amplifiers for Quantum Computers

Abstract

This report presents the design and simulation of an on-chip diplexer intended for Traveling- Wave Parametric Amplifier (TWPA) applications. The device targets a 4–8 GHz source signal and a 10 GHz pump frequency, with the objective of maximizing the pump suppression and minimizing the insertion loss for the source signal. A cut-off frequency of 9 GHz was established to satisfy matching criteria of S11 < −20 dB and pump suppression of S21 < −25 dB. The final series-first diplexer design successfully meets the pump suppression requirement of at least −25 dB at 10 GHz but does not fully maintain the −20 dB matching across the entire bandwidth. Simulations performed in both ADS and Sonnet confirm that, despite not meeting the matching goal, the diplexer likely maintains acceptable performance, suggesting that the initial matching requirement may have been overly stringent. As the design has not yet been fabricated, practical measurements are pending. The close agreement between the ADS and Sonnet simulations demonstrates that fast preliminary simulations in ADS can effectively guide and streamline the design process. Future work involves fabricating the device, measuring its real-world performance, and iterating the design. An elliptical filter approach is proposed for subsequent design iterations to potentially achieve improved matching and suppression.