High-performance transistors with twodimensional semiconductor nanoribbons

Abstract

The progressive miniaturization of transistors has been the engine of the modern information revolution. While both gate lengths and channel thicknesses have been scaled into the sub-20 nm regime in state-of-the-art silicon gate-all-around nanosheet architectures, the channel width, the last unscaled dimension in transistors, has remained constrained above ∼40-50 nm. This “width-scaling wall” arises from dangling-bond trap states, lateral charge depletion, and edgeroughness scattering that collectively suppress drive current as channel widths are reduced, fundamentally limiting the transistor integration density. Breaking this wall is one of the most consequential open challenges in semiconductor device physics. This master’s thesis presents the experimental demonstration that two-dimensional semiconductor nanoribbon transistors overcome the width-scaling wall and operate in an edge-enhanced transport regime. A high-fidelity top-down lithographic nanofabrication strategy enabled the fabrication of monolayer and bilayer molybdenum disulfide (MoS2) nanoribbon transistors with channel widths as narrow as 15 nm. In contrast to the conventional semiconductor scaling rule that associates degraded current density with reduced channel width, atomically thin monolayer and bilayer MoS2 nanoribbon transistors in this work demonstrate enhancements in on-current density of up to 230% and 170%, respectively, followed by saturation for channel widths approaching 15 nm. These ultranarrow transistors achieve on/off ratios of 106 with channel lengths as short as 50 nm. In addition, enhanced mobility and threshold-voltage stability suggest reduced edge scattering and depletion resulting from improved electrostatic control. The demonstrated monolayer and bilayer MoS2 nanoribbon transistors achieve on-current densities up to ∼300-400 μAμm−1 in the 15-30 nm channel width regime. These findings provide an experimental foundation for channel width scaling to realize the ultimate scaling of high-performance transistor technologies.