Space-Time Adaptive Processing in FPGA

Abstract

Space-Time Adaptive Processing (STAP) enables very high performance radar processing but comes at a high price of computational requirements and can reach up to hundreds of TFLOPS. This makes it difficult to implement for limited spaces with low power consumption. This thesis investigates the possibility to implement STAP in an FPGA with focus on the detection algorithm known as Kelly's Generalised Likelihood Ratio Test (GLRT). One of the main goals of the implementation was scalability and parallelism since the technology of the present time is not power efficient enough. A solution that is scalable and can utilize parallelization is possible to distribute over a larger device when the technology is present. Another goal was the comparison of fixed and floating point number representation in terms of performance and power. The final design was implemented on a Xilinx Virtex-7 FPGA for both single precision floating point and 32 bit fixed point number representation. Three different design solutions were implemented. The final design resulted in a performance of 23.2 GFLOPS/W for the floating point design, 34.3 GFIOPS/W for the fixed point implementation using IP cores and 39.3 GFIOPS/W for the pipelined solution. Existing performance results from NVIDIA GTX 260 GPU the performance is 5.1 GFLOPS/W and for the FPGA co-processor Anemone the number is 19.2 GFLOPS/W. The solution is scalable and the conclusion is that it is likely that an FPGA solution would be suitable for STAP when the technology exist. However, the support for floating point in the tools need further development to be competitive with the fixed point implementations.