Power Integrity Analysis of AVR Processor

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/131944
Download file(s):
File Description SizeFormat 
131944.pdfFulltext1.02 MBAdobe PDFView/Open
Type: Examensarbete för masterexamen
Master Thesis
Title: Power Integrity Analysis of AVR Processor
Authors: Ravi, Badri Narayanan
Abstract: In the deep submicron era, the power supply voltage to the logic devices should be well within the bound limits. The degradation of power affects the timing closure of the chip, thus affecting the performance. In this thesis, the analysis flow used in previous study is modified to make it generic to all series of AVR processors. By extracting a power grid model and subjecting it to extensive simulations, the issue causing the power degradation is analysed. Analysis results show that the cause for the first voltage drop is due to two factors, that is, current loads and resistive property of the metal wires. The first overshoot after voltage drop increases for wider metal wires compared to lesser width of metal wires. Nodes of the power grid having large voltage drop show that on-chip self inductance can no longer be ignored in designing power distribution networks for high frequency circuits.
Keywords: Datorteknik;Computer Engineering
Issue Date: 2010
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/131944
Collection:Examensarbeten för masterexamen // Master Theses



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.