Optimized Register File Implementation

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/143673
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Type: Examensarbete för masterexamen
Master Thesis
Title: Optimized Register File Implementation
Authors: Hasan, Ali
Vijayashekar, Akshay
Abstract: The register file is a critical component in any CPU design. As it is accessed almost every cycle, it contributes significantly to key chip characteristics. It is a vital component to optimize for best performance, area and power dissipation. The purpose of this thesis is to implement a full custom, low power and area efficient register file for an Atmel 32-bit microcontroller. The benchmark design is a flip-flop based register file. This thesis work is carried out in two phases – Literature study phase and Implementation phase. During the literature study phase, a number of cell topologies for SRAM based register files were explored. A few different cell topologies were selected for implementation and the power dissipation was estimated. Apart from different cell topologies, different register files architectures such as time-multiplexed and partitioned register files have been implemented. Simulation results show that significant area and power savings can be achieved by designing a SRAM based full custom register file, instead of making a design based on flip-flops.
Keywords: Information Technology;Informationsteknik
Issue Date: 2011
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/143673
Collection:Examensarbeten för masterexamen // Master Theses



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