Hard-decision Staircase Decoder in 28-nm Fully-Depleted Silicon-on-Insulator
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Typ
Examensarbete för masterexamen
Master Thesis
Master Thesis
Program
Embedded electronic system design (MPEES), MSc
Publicerad
2016
Författare
Hurtic, Elma
Lillmaa, Henri
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
The continuous advancements in optical communication channels have propelled the development of new error-correcting codes, e.g., staircase codes, which belong to a class of hard-decision algebraic codes. The staircase code is a new in-line error-correcting code that promises near-capacity performance. In this Master’s Thesis BCH component codes and staircase codes are analysed in MATLAB. A bit-parallel BCH component code decoder is described in VHDL and synthesised in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) library. Based on synthesis and simulation, the area and power consumption of staircase decoders for 100 Gbps throughput are estimated.
Beskrivning
Ämne/nyckelord
Informations- och kommunikationsteknik , Data- och informationsvetenskap , Information & Communication Technology , Computer and Information Science