Hard-decision Staircase Decoder in 28-nm Fully-Depleted Silicon-on-Insulator

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dc.contributor.authorHurtic, Elma
dc.contributor.authorLillmaa, Henri
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T13:55:48Z
dc.date.available2019-07-03T13:55:48Z
dc.date.issued2016
dc.description.abstractThe continuous advancements in optical communication channels have propelled the development of new error-correcting codes, e.g., staircase codes, which belong to a class of hard-decision algebraic codes. The staircase code is a new in-line error-correcting code that promises near-capacity performance. In this Master’s Thesis BCH component codes and staircase codes are analysed in MATLAB. A bit-parallel BCH component code decoder is described in VHDL and synthesised in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) library. Based on synthesis and simulation, the area and power consumption of staircase decoders for 100 Gbps throughput are estimated.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/238595
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectInformations- och kommunikationsteknik
dc.subjectData- och informationsvetenskap
dc.subjectInformation & Communication Technology
dc.subjectComputer and Information Science
dc.titleHard-decision Staircase Decoder in 28-nm Fully-Depleted Silicon-on-Insulator
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
local.programmeEmbedded electronic system design (MPEES), MSc
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