Design of a phase locked loop for 60 GHz/ 30 GHz signal generation in 22nm FDSOI technology for wireless transceivers

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/256662
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Type: Examensarbete för masterexamen
Master Thesis
Title: Design of a phase locked loop for 60 GHz/ 30 GHz signal generation in 22nm FDSOI technology for wireless transceivers
Authors: Bhuvanendran Sathiabhama, Sajeendran
Abstract: Phase Locked Loops (PLLs) are fundamental components in communication systems used in frequency synthesis, carrier recovery and modulation. Massive Multiple Input Multiple Output (MIMO) based millimeter wave communication systems demand reference frequencies with high spectral purity. Low power implementation of PLLs in deep submicron CMOS processes is essential in the current market demand for integrated transceivers for future communication systems like 5G. This thesis deals with the design of a 60 GHz PLL in 22nm FDSOI technology for use in 5G transceiver systems.
Keywords: Informations- och kommunikationsteknik;Data- och informationsvetenskap;Information & Communication Technology;Computer and Information Science
Issue Date: 2019
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/256662
Collection:Examensarbeten för masterexamen // Master Theses



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