Design of a phase locked loop for 60 GHz/ 30 GHz signal generation in 22nm FDSOI technology for wireless transceivers
Ladda ner
Typ
Examensarbete för masterexamen
Master Thesis
Master Thesis
Program
Embedded electronic system design (MPEES), MSc
Publicerad
2019
Författare
Bhuvanendran Sathiabhama, Sajeendran
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
Phase Locked Loops (PLLs) are fundamental components in communication systems used in frequency synthesis, carrier recovery and modulation. Massive Multiple Input Multiple Output (MIMO) based millimeter wave communication systems demand reference frequencies with high spectral purity. Low power implementation of PLLs in deep submicron CMOS processes is essential in the current market demand for integrated transceivers for future communication systems like 5G. This thesis deals with the design of a 60 GHz PLL in 22nm FDSOI technology for use in 5G transceiver systems.
Beskrivning
Ämne/nyckelord
Informations- och kommunikationsteknik , Data- och informationsvetenskap , Information & Communication Technology , Computer and Information Science