Clock Synchronisation Method Over Bandwidth-Limited CAN-Bus
Typ
Examensarbete för masterexamen
Program
Embedded electronic system design (MPEES), MSc
Publicerad
2021
Författare
Mathiesen, Christoffer
Kvist, David
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
Clock synchronisation is an integral part of systems where the ordering of events is
needed. While implementations exist on the CAN-bus to provide clock synchronisa tion, additional improvements are needed to provide a robust protocol while limiting
the amount of traffic used in a system. Many solutions rely on the entire system
architecture to be known or a timekeeper be preassigned before the start of the sys tem, thus limiting the adaptability and/or scalability of the protocol. Here we aim
to implement a solution that does not depend on knowledge of the number of nodes,
and where each node can independently or collectively retain timekeeping regardless
of what happens to the timekeeping master device. The timekeeping master node
should not be necessary to be preassigned, instead, the system should be capable
of arbitrating the master node at startup and achieve synchronicity. Furthermore,
nodes should be able to arrive and leave an active system at any moment, also
known as being hot-plug enabled. The nodes are envisioned to be of limited com putational ability and not necessarily be constructed with the same hardware. As
such a protocol capable of handling counter rollover and devices with different local
oscillator frequencies is to be designed. While a lot of design insight was gained
and a demonstrator system was partially implemented in hardware the task was
underestimated and ultimately not completed. A complete HDL-implementation
might be very possible, but it might not be better than a system comprised of both
hardware and software.
Beskrivning
Ämne/nyckelord
Timekeeping Synchronisation , CAN , FPGA , Master-arbitration