Evaluation of Fault-Tolerance Methods in Commercial Off-The-Shelf FPGAs Used in Harsh Environments

Abstract

The increased desire for space-based services has led companies to develop the systems using cheaper electronics while providing a large processing power. It poses a challenge where companies must consider that the system should be radiation resistant. The purpose of the thesis is to explore three fault tolerance methods and implement two in the NOEL-V processor, which runs on a commercial-off-the-shelf SRAM FPGA followed by a concept of fault fault injection in the processor during runtime. After testing the system with the created fault injection, triple modular redundancy (TMR) and lockstep were implemented to compare their clock rate, power consumption, and resource utilisation with a base design. The results show a functioning concept of fault injection and that the lockstep method consumes a moderate amount of resources and power while maintaining the same clock rate as the base design. Findings suggest that the current fault tolerance solution should be expanded to lower levels of the processor and increasing support for the fault injection to target specific registers.