Linking event-based simulations in process simulate with Supremica to perform formal verification sequences of operations at VCC
dc.contributor.author | Modig, Christoffer | |
dc.contributor.author | Westman, Fredrik | |
dc.contributor.department | Chalmers tekniska högskola / Institutionen för signaler och system | sv |
dc.contributor.department | Chalmers University of Technology / Department of Signals and Systems | en |
dc.date.accessioned | 2019-07-03T12:07:56Z | |
dc.date.available | 2019-07-03T12:07:56Z | |
dc.date.issued | 2008 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12380/69027 | |
dc.language.iso | eng | |
dc.relation.ispartofseries | Ex - Institutionen för signaler och system, Chalmers tekniska högskola : EX016/2008 | |
dc.setspec.uppsok | Technology | |
dc.subject | Elektroteknik och elektronik | |
dc.subject | Electrical Engineering, Electronic Engineering, Information Engineering | |
dc.title | Linking event-based simulations in process simulate with Supremica to perform formal verification sequences of operations at VCC | |
dc.type.degree | Examensarbete för masterexamen | sv |
dc.type.degree | Master Thesis | en |
dc.type.uppsok | H |