Linking event-based simulations in process simulate with Supremica to perform formal verification sequences of operations at VCC

dc.contributor.authorModig, Christoffer
dc.contributor.authorWestman, Fredrik
dc.contributor.departmentChalmers tekniska högskola / Institutionen för signaler och systemsv
dc.contributor.departmentChalmers University of Technology / Department of Signals and Systemsen
dc.date.accessioned2019-07-03T12:07:56Z
dc.date.available2019-07-03T12:07:56Z
dc.date.issued2008
dc.identifier.urihttps://hdl.handle.net/20.500.12380/69027
dc.language.isoeng
dc.relation.ispartofseriesEx - Institutionen för signaler och system, Chalmers tekniska högskola : EX016/2008
dc.setspec.uppsokTechnology
dc.subjectElektroteknik och elektronik
dc.subjectElectrical Engineering, Electronic Engineering, Information Engineering
dc.titleLinking event-based simulations in process simulate with Supremica to perform formal verification sequences of operations at VCC
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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