Deep Integration of a Memory Encryption Engine in Modern Processor Designs

dc.contributor.authorSÖRQVIST, IVAR
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data och informationstekniksv
dc.contributor.examinerLarsson-Edefors, Per
dc.contributor.supervisorStenström, Per
dc.date.accessioned2021-07-13T11:35:37Z
dc.date.available2021-07-13T11:35:37Z
dc.date.issued2021sv
dc.date.submitted2020
dc.description.abstractKeeping execution of data secure from potential attackers is a major concern today, especially in cloud computing. Intel SGX is one example of such a trusted execution environment, utilising isolation of data on-chip memory and encryption off-chip. However, numerous publications have been published exploiting its vulnerabilities with different types of side-channel, Spectre and Meltdown attacks. In this thesis, we propose a relocation of the encryption stage deeper into a processor’s memory hierarchy which could be a potential solution for a more secure system. We introduce two systems: first moving the encryption stage to before the shared last-level cache, second encrypting before the first level data cache with an added dedicated cache for cryptography. For the second different placements of prefetching are investigated further. Through simulations using the gem5 simulator, we show that these systems suffer minor performance losses compared to using no encryption at all.sv
dc.identifier.coursecodeDATX05sv
dc.identifier.urihttps://hdl.handle.net/20.500.12380/303787
dc.language.isoengsv
dc.setspec.uppsokTechnology
dc.subjectMastersv
dc.subjectthesissv
dc.subjectprocessorsv
dc.subjectcryptographysv
dc.subjectencryptionsv
dc.subjectenginesv
dc.subjectMEEsv
dc.subjectsimulationsv
dc.subjectgem5sv
dc.subjectTEEsv
dc.titleDeep Integration of a Memory Encryption Engine in Modern Processor Designssv
dc.type.degreeExamensarbete för masterexamensv
dc.type.uppsokH
local.programmeEmbedded electronic system design (MPEES), MSc
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