Dynamic fault generator for simulating gracefully degradable components
Examensarbete för masterexamen
Embedded electronic system design (MPEES), MSc
Transistors dimensions are scaling down according to Moore’s Law making integrated circuits much prone to failures. To help study the reliability of such complex systems, the aim of this thesis is to develop a high-level tool that inject faults dynamically on a gracefully degradable adaptive system during its lifetime. Our developed tool operates in closed-loop with the rest of the experimental setup, receiving feedback parameters that have an influence on the prediction routine, such as the components’ utilization rates. Additionally, the tool is able to consider transistor wearout effects in the fault prediction routine, such as Negative Bias Temperature Instability (NBTI). Furthermore, we were able to examine different degradable aspects of complex systems using different fault scenarios. For instance we studied the capacity degradation over time of the 3-D stacked DRAM Hybrid Memory Cube (HMC) and found that the remaining memory capacity after 10 years is around 86% considering normal failure rates and around 77% considering pessimistic failure rates. We also studied the degradation of a reconfigurable processor array in terms of number of operating processors over time for array sizes 8-by-7 and 4-by-8, and determined the best array size given the failure rate and expected mission time.
Informations- och kommunikationsteknik , Data- och informationsvetenskap , Information & Communication Technology , Computer and Information Science