Clock recovery algorithm in Circuit Emulation Service (CES)
Examensarbete för masterexamen
The clock recovery function of a communications systems was studied along with the performance requirement of that system. The thesis focused on the phase locked loop (PLL) that is used for clock recovery, specifically the low pass filter (LPF) used by the PLL. Given the lack of a frequency response specification to be used as a starting point for the LPF design, a simulation tool that simulates and predicts the system’s performance in terms of maximum time interval error (MTIE) was developed. This tool was subsequently used to design alternative low pass filters for the PLL. By examining the predicted performance, a filter design was proposed, implemented and integrated in an FPGA based design. The filtering algorithm was run in the real system and evaluated. It was concluded that in a system that utilizes a packet selection algorithm (PSA), a filtering solution that combines a proportional-integral (PI) controller with an added infinite impulse response (IIR) filter can comply with the required specification.
FPGA , clock-recovery , CES , digital filter , ADPLL