Implementation and Evaluation of Last-Level Cache Partitioning

Abstract

With parallel applications executing on a multiprocessor comes the problem of interference due to resource sharing between processor cores. The contention of resources can lead to a lack of fairness between the cores. Furthermore, having a shared last-level cache introduces destructive interference in the form of cores evicting other cores’ cache blocks. Cache partitioning is a method to solve these problems, which has both been extensively researched in academia and implemented in end-products in industry. In this thesis we will analyze the effects of cache partitioning in terms of performance and overhead. We implement six replacement algorithms and a cache design in RTL, all supporting way-based cache partitioning. These are then used in a test bench where execution is simulated by feeding the test bench memory traces extracted from the L2-accesses of benchmark programs from the SPEC-CPU-2006 benchmark suite.

From our results we conclude that way-based partitioning can easily be implemented with little overhead. We also show that in some cases, the increase of shared ways available to an application does not offset the effect of interference, which leads to worse performance of the application. From the aforementioned memory traces we generate reuse histograms to analyze the expected cache behaviour of the simulated benchmark programs. This gives us the ability to predict a good way to partition the cache, based on the running applications.