Impact of Pin Orientation on Routing Regularity of HPM Architectures

Abstract

In the context of regular arithmetic circuits, the effect of pin placement on the quality of layout and routing is not well understood. Current methodologies depend on library-based flows to design such circuits. However, the benefits of regularity are lost in the process of automated place and route techniques employed by these methodologies. As process technologies grow smaller, this will have a large effect on the yield and variability. Enforcing regularity to combat variability is being advocated in the form of restricted design rules. This thesis attempts to develop a methodology to implement customized pin orientations for the cells. These cells are used in the design to harness the benefits of regularity and in the process, mitigate variability. HPM multiplier is taken as a case study and different pin orientations are tried out for the cells constituting rectangular PPRT of the multiplier. The tool-set to be used for this project include Cadence Virtuoso for implementing the standard cell layouts, Cadence Encounter Library Characterizer to perform characterization of the implemented layouts and Cadence SoC Encounter to implement the HPM multiplier using the customized standard cells.