Testing infrastructure for experimental chips

Abstract

As transistor sizes shrink and performance requirements of experi-mental chips increase, verifying and testing the chips becomes more and more complex. One traditional way of testing is generating external input signals to test the chip and evaluating the testing results outside the chip but this is a costly approach. A on-chip testing approach, in which the generation of input signals and evaluation of output signals are integrated with the chip, would be an interesting alternative. This low-cost approach has been used in testing a recent Forward-Error-Correction chip (FEC-chip). The aim of this thesis project is to generalize the testing evaluation setup used in testing experimental chips to make it more effective and efficient. In this project, a testing system, in which an MCU can read/write data to/from experimental chips via an SPI interface and a CRC error detection scheme was used to improve the data transaction reliability of the testing system, was designed and implemented. A PCB supporting the new testing system was designed. The results of the thesis project can be used to testing other designed chips with its low-cost and fast data transmission speed features.