Fast performance estimations for vector architectures using qemu-plugins

Abstract

New applications requiring high computations have arrived (AI, HPC, Cybersecurity etc..) leading to algorithm-hardware configuration exploration side-by-side. This has created the need for tools that can quickly navigate (and thereby prune) the wide design space to be explored by providing performance estimates in a short time-span. This thesis develops/extends a tool to provide performance estimates for an algorithm on a given hardware configuration having vector processing unit and cache hierarchy. It further validates the accuracy of results upon comparison with golden reference.