Statistics Monitor Design for Data Flow and Performance Analysis of an AMBABased SoC System

Abstract

Today’s advanced system-on-chip (SoC) contains multiple intellectual properties (IPs) and technology with billions and billions of transistors all packed in an ultrasmall form factor. All of it needs to perform flawlessly meeting demanding power and performance goals on tight schedules. Hence the complexity of SoC is sharply increasing. However, the performance of the system is not scaling linearly with the number of gate count. Henceforth, understanding the internal, dynamic behavior and having a constructive utilization of resources is critical in SoC design. In this thesis, we present a statistics monitor which is capable of monitoring data flow and performance metrics of AMBA-based SoC systems. The study considers different performance parameters such as system-level throughput, latency, bus efficiency, etc. The statistics monitor outputs such statistics data. The data obtained from the monitor unit provide insights into the SoC design, by assisting in the detection of performance bottleneck of the system.