A scalable manycore simulator for the Epiphany architecture
Examensarbete för masterexamen
The core count of manycore processors increases at a rapid pace; chips with hundreds of cores are readily available, and thousands of cores on a single die have been demonstrated. A scalable model is needed to be able to effectively simulate this class of processors. We implement a parallel functional network-on-chip simulator for the Adapteva Epiphany architecture, which we integrate with an existing single-core simulator to create a manycore model. To verify the implementation, we run a set of example programs from the Epiphany SDK and the Epiphany toolchain test suite against the simulator. We run a parallel matrix multiplication program against the simulator spread across a varying number of networked computing nodes to verify the MPI implementation. Having a manycore simulator makes it possible to develop and optimize scalable applications even before the chips for which they are designed become available. The simulator can also be used for parameter selection when exploring richer hardware design spaces.
Simulation , Functional Simulator , Manycore , Network-on-Chip , Adapteva , Epiphany , eMesh , Shared Memory , MPI , Process-level parallelism , GDB