Evaluation of synchronization methods in multi-clock domain systems
Examensarbete för masterexamen
Modern SoC employ multi clock domains on the same die, this is because each block of the system may require different clock voltage and frequencies which results to economical benefits. Systems with embedded processors generally requires high speed clocks, it becomes very difficult to maintain one global clock connected all sub blocks to meet the speed requirement of the system. One way to overcome this difficulty is to employ GALS clock system. In GALS clock system each block/island is locally synchronous and connected to other blocks by an asynchronous interconnect system. Synchronization bridge is required in between multiple clock domains to avoid the risk of metastability to those signals which are prone to frequent transitions, and are propagated between two multiple clock domains. In this project, the bridges are applied to the Wishbone bus in which two clocks differs from each other, in frequency and phase. Each clock is separately applied for Wishbone Master and Wishbone Slave thus acts as two as different clock domain systems w.r.t signals that are propagated between them. Bridges such as two flip flop and locally delayed latching are designed and implemented. The performance is evaluated and compared. Further the bridges are processed to standard VLSI place and route.
Datavetenskap (datalogi) , Computer Science