Hybrid GaN-SiC 3-Level Inverter Topologies for High-Performance Power Conversion

Abstract

The electrification of road transport demands power electronics that are simultaneously efficient, compact, and reliable across a wide range of operating conditions. This thesis investigates the loss performance of four inverter topologies the three-level Active Neutral- Point-Clamped (3L-ANPC), the three-level Sparse Neutral-Point-Clamped (3L-SNPC), the three-level T-type Neutral-Point-Clamped (3L-TNPC), and the two-level inverter as a reference using wide-bandgap semiconductors from the SiC and GaN(GIT) families, as well as hybrid SiC-GaN(GIT) device combinations. All configurations are evaluated through parametric PLECS simulations across a switching frequency of 10–100 kHz, output peak phase current 40–50 A, and an ambient temperature of 45–85°C, representative of an 800 V EV drivetrain. The hybrid SiC-GaN(GIT) SNPC achieves the lowest total losses of any configuration tested 175.2 W at the reference operating point was achieved for 13.5kW transmitted power, approximately 20% lower than the ANPC configuration, approximately 20% lower than the hybrid SiC-GaN(GIT) TNPC in same device configuration. In the 3L-ANPC, the SiC-GaN(GIT) hybrid configuration achieves the lowest total losses among all five device configurations across all three parametric sweeps frequency, current, and temperature. It combines GaN’s low switching losses with SiC’s stable conduction performance, delivering a consistently flat and low loss profile that no single-technology configuration can match. For the T-type inverter, the hybrid SiC–GaN(GIT) reduces switching losses compared with the full-SiC configuration, particularly at higher switching frequencies. However, due to the device characteristics and current commutation behavior of the selected configuration, the reduction in switching losses is insufficient to compensate for the increased conduction losses, which become dominant under the investigated operating conditions. The results demonstrate that inverter topology, device property, and device placement configuration must be optimised jointly the right device in the wrong position will prevent the topology from delivering its best outcome.