Coded pilot synchronization in wide band sub-THz communication systems

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Future wireless communication systems operating in the sub-terahertz (sub-THz) frequency range (100–300 GHz) offer extremely large bandwidths, enabling ultra high data rates for next-generation applications such as wireless backhaul, chip-to chip communication, and sensing. However, carrier synchronization (CS) in such systems remains a major challenge due to large carrier frequency offsets (CFO), se vere phase noise, and the impracticality of using ultra-high-speed analog-to-digital converters (ADCs) for wideband signal processing. This thesis proposes a low cost analog-digital hybrid synchronization method us ing a low-power pseudo-noise (PN) coded pilot that can be detected even at very low power levels using matched filtering. A PN-coded pilot is embedded within the transmitted signal (a single wideband signal) at power levels up to 30-50 dB below the data signal. At the receiver, the pilot is extracted using a narrowband filter and processed with a PN-based matched filter to achieve significant processing gain, enabling reliable detection using low-speed ADCs. A hybrid analog–digital phase-locked loop (PLL) architecture is proposed, where carrier frequency and phase estimates obtained from PN correlation are used to control the local oscillator. The system is first validated through MATLAB sim ulations under realistic impairments, including large CFO and strong phase noise. Results demonstrate successful carrier recovery and reliable detection of pilot sig nals buried down to 30 dB below the data signal. The proposed approach is further implemented on an FPGA platform to evaluate real-time performance and hardware feasibility. The results show that PN-coded pilot synchronization is a promising solution for en abling practical, low-complexity carrier recovery in ultra-wideband sub-THz systems without requiring high-speed data converters.

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fixed-point arithmetic, VHDL design, DPLL, NCO, signal processing, wireless communication systems

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