Energy Efficient Digital Signal Processing in Radar Receiver Systems

Abstract

The number of digital receiver channels in today's radar systems are increasing rapidly. More receiver channels leads to more hardware which causes the power consumption to rise. Meanwhile more channels offers higher system performance. Therefor it is desirable to find a solution that reduces the power consumption, and allows implementation of more channels. Radar systems are commonly implemented in FPGAs and we have evaluated several different methods to improve the efficiency and reduce the amount of hardware needed, including efficient hardware structures, and increased hardware utilization. Implementations with direct FIR filters are used to benchmark the improved implementations and are considered a reference system. Based on an extensive literature study several simulations, including performance estimations, are performed. A subset of the simulations of each design are of particular interest and are further evaluated through hardware implementation in a Xilinx Kintex 7 FPGA. The power consumption of each implementation is measured, and based on the results the performance for a single demodulator chain is calculated. An improved system implementation is presented, where the FIR filter is replaced with a CIC-FIR filter combination. The filter implementation offers more than 80 dB attenuation whilst reducing the power consumption, and using a fraction of the hardware compared to the reference system. With the suggested implementation the system can run at 500 MHz. At the cost of a small hardware penalty with slightly increased power consumption the implementation is capable of more than 100 dB attenuation. Finally, we present some areas that can be further investigated to possibly reduce the power consumption even further, and some actions that can be taken that might further improve the performance of the suggested system.