Implementation and Verification of a 7-Stage Pipeline Processor

Abstract

This report details the implementation of a 7-stage processor pipeline using VHDL. The report excludes discussion on instruction and data caches. The pipeline stages are balanced with respect to timing. The pipeline design is verified using embedded microprocessor benchmarks. The synthesized pipeline design is evaluated in terms of timing, area, and power. Implementation and evaluation of the branch predictors are emphasized, as they are vital part of a processor pipeline. Prior to branch predictor implementation, several branch predictor configurations have been evaluated, for their performance, through simulations using SimpleScalar tool. Based on the simulation results, few best performing predictors have been implemented and verified by integrating them into a processor pipeline. The pipeline design is synthesized using Cadence Encounter RTL compiler in order to extract area and power estimates. Based on the synthesis results, evaluation of the pipeline and its function units has been carried out. The multiplier and the branch predictor unit are identified as the most critical with respect timing. Solutions have been suggested to improve the timing balance between the pipeline stages. It has also been evaluated that even though the branch predictors contribute for a significant improvement in the performance of a pipeline, they also account for 45% of total area and 65% of total power of the pipeline. The effect of caches on the pipeline timing, area, and power is not considered for evaluations.