FPGA prototyping of the MSP430F5172

Abstract

The aim of this master thesis is to develop a working FPGA prototype of the MSP430F5172. This report deals with the standard steps of FPGA recoding. It relates the implementation results to the FPGA logic primitives and an introduction to such logic primitives is provided when such a discussion is presented. So the result and the theory are interconnected throughout the content of the report. It also presents a discussion on the extensive spectrum of tools involved in the FPGA implementation process from EDIF netlist generation to the final bitstream generation as well as analysis tools like timing analyzer. An overview of the principles involved in the implementation process provides a better understanding of the operation of the tools. In addition many features of the tools explored during the execution of the thesis is documented that enables the reader to reduce the learning curve involved in implementing such a project in the future. The device utilisation for the MSP430F5172 prototype on the Virtex5 LX110 was about 25%. In spite of such a moderate device utilisation the runtimes were as high as 3 hours which can give an idea of the complexities involved in the RTL code of modern microprocessors. Issues faced in the course of the thesis are also presented and discussed. Procedures and principles that can help overcome this issues are also presented. Finally, the FPGA prototype is subjected to basic functional tests. The results and code example is also provided.