Investigation of high performance configurations on the Evolved Packet Gateway
| dc.contributor.author | Chatziadam, Georgios | |
| dc.contributor.author | Mebrahtu Birhanu, Tsigabu | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data och informationsteknik | sv |
| dc.contributor.examiner | Tsigas, Philippas | |
| dc.contributor.supervisor | Duvignau, Romaric | |
| dc.contributor.supervisor | Walulya, Ivan | |
| dc.date.accessioned | 2021-04-21T06:29:23Z | |
| dc.date.available | 2021-04-21T06:29:23Z | |
| dc.date.issued | 2020 | sv |
| dc.date.submitted | 2020 | |
| dc.description.abstract | Modern servers today are based on multi-socket motherboards to increase their power and performance figures. These setups provide CPU interconnection through a high speed bus. If processes on one CPU need access to memory or devices local to another CPU, they need to traverse this bus and this adds a delay to the execution time. This is where the concept of Non-Uniform Memory Access (NUMA) presents as a solution. Every socket with its local memory is considered a node, that is locked and processes are not allowed to migrate. This means that loading instructions has low latency, but they can also access the main memory connected to the other NUMA nodes at a given penalty cost. The latest CPUs such as the EPYC series from AMD are using this concept even within the processor module, and there is no possibility to avoid taking into account NUMA aspects. There has been a plethora of benchmarks to analyze the impact of NUMA node architecture on different processors. In this work, we have used the Packet Gateway of the Evolved Packet Core (EPC) as a test case to investigate the effectiveness of NUMA architecture on Intel processors on a virtual large-scale distributed production system with high performance requirements. On the virtualization setups, di erent CPU pining and deployment strategies are used, while Packet Per Second (pps) is the preferred performance indicator in systems like the Evolved Packet Gateway (EPG).We further describe and analyze different scenarios, combining CPU pinning and process placement, within the virtual machines running the EPG. | sv |
| dc.identifier.coursecode | DATX05 | sv |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/302313 | |
| dc.language.iso | eng | sv |
| dc.relation.ispartofseries | CSE 20-03 | sv |
| dc.setspec.uppsok | Technology | |
| dc.subject | NUMA | sv |
| dc.subject | EPG | sv |
| dc.subject | Computer Science | sv |
| dc.subject | Engineering | sv |
| dc.subject | Project | sv |
| dc.subject | Thesis | sv |
| dc.title | Investigation of high performance configurations on the Evolved Packet Gateway | sv |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.uppsok | H | |
| local.programme | Computer systems and networks (MPCSN), MSc |