Design and Implementation of a Network-on-Chip based Embedded System-on-Chip
| dc.contributor.author | Strikos, Panagiotis | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data och informationsteknik | sv |
| dc.contributor.examiner | Larsson-Edefors, Per | |
| dc.contributor.supervisor | Sourdis, Ioannis | |
| dc.date.accessioned | 2021-11-03T10:30:50Z | |
| dc.date.available | 2021-11-03T10:30:50Z | |
| dc.date.issued | 2021 | sv |
| dc.date.submitted | 2020 | |
| dc.description.abstract | Today, the demand for more computing power has led embedded computing systems to become more complex than ever. As a result, a wide range of multi and many-core System-on-Chip (SoC) architectures has been proposed. Traditionally, the bus has been used as an interconnection mechanism in many embedded systems, including the space domain. As the need for extensive processing rises though, and while multi and many-core architectures become a necessity, the bus often fails to accommodate the communication needs of such systems. By lacking the ability to scale well, buses introduce a bottleneck in the communication needs of the system’s throughput. On the other hand, Networks-on-Chip (NoC) have emerged to become a paradigm for complex architectures, since they offer a scalable communication solution, serving as a replacement to the traditional bus-based interconnections. This thesis studies the upgrade of a bus-based embedded System-on-Chip by replacing its AMBA 2.0 AHB bus with an existing Network-on-Chip. To achieve that, a network interface is designed, a unit responsible for communicating with both the AHB components and the NoC, while leaving the original functionality of the systems intact. An in-depth analysis of a network interface is performed, and at the same time, a modified NoC-based version of the systems is presented featuring FastTrackNoC routers. Our evaluation shows that compared to the baseline bus-based System on-Chip, the NoC-based one, improves communication latency from 44% and up to 97%, while resulting in a 1.68 × −37.5× higher throughput. At the same time, the proposed system increases the area overhead by a factor of 7× −72×. Although the system was only analyzed in simulation, it also has the potential to be implemented in hardware, as RTL descriptions for both the NoC and the SoC have been developed. | sv |
| dc.identifier.coursecode | DATX05 | sv |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/304316 | |
| dc.language.iso | eng | sv |
| dc.setspec.uppsok | Technology | |
| dc.subject | System-on-Chip | sv |
| dc.subject | Network-on-Chip | sv |
| dc.subject | Network Interface | sv |
| dc.subject | AMBA | sv |
| dc.subject | AHB | sv |
| dc.subject | FastTrackNoC | sv |
| dc.subject | On-Chip Interconnect | sv |
| dc.title | Design and Implementation of a Network-on-Chip based Embedded System-on-Chip | sv |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.uppsok | H | |
| local.programme | Embedded electronic system design (MPEES), MSc |