Power Estimation for DSP Components for Fiber-Optic Communication Systems
| dc.contributor.author | Chelini, Lorenzo | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers) | sv |
| dc.contributor.department | Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers) | en |
| dc.date.accessioned | 2019-07-03T14:28:14Z | |
| dc.date.available | 2019-07-03T14:28:14Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | In this thesis, we propose and examine a power estimation method for Finite Impulse Response (FIR) filters used in short-reach fiber-optic communication systems, where limitations on size and power consumption start to become a critical design metric. We first implement a library of optimized FIR filter netlists that can satisfy the high performance required for optical communication. Second, we analyze the FIR filter implementations and we propose a new activity-based macromodeling strategy. More precisely, the model makes use of the switching activity of the logic inputs to estimate the power consumption at architectural level. Following the taxonomy available in the literature, our estimator tool can be classified as a cycle-accurate macromodel and it consists of two phases: characterization and power estimation. The characterization is a fully automated procedure that takes as input a netlist and generates power values using gate-level simulations. Those values are classified accordingly to the Hamming distance of each input pair and tabulate in pre-defined structures. Characterization needs to be done only once for each filter architecture at a reasonably strict timing constraint. The power estimation takes as inputs the predefined tables, input trace, and produces power values in a cycle-by-cycle manner. The average power is computed summing up the per-cycle power values and divide the sum by the duration of the input trace expressed in clock cycles. A key strength of our proposed solution is that it provides results within seconds since we do not need to perform additional simulations during power estimation. For the operand word-lengths tested the error was below 15 percent for most of the circuits. The only exception was for the 8-bit input and 6-bit coefficient and the 8-bit input and 10-bit coefficient where the error was above 15 percent. The results are promising and demonstrate the practicability and validity of this approach. | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/249942 | |
| dc.language.iso | eng | |
| dc.setspec.uppsok | Technology | |
| dc.subject | Informations- och kommunikationsteknik | |
| dc.subject | Data- och informationsvetenskap | |
| dc.subject | Information & Communication Technology | |
| dc.subject | Computer and Information Science | |
| dc.title | Power Estimation for DSP Components for Fiber-Optic Communication Systems | |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.degree | Master Thesis | en |
| dc.type.uppsok | H | |
| local.programme | Embedded electronic system design (MPEES), MSc |
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