Electrical and Thermal Optimization of Inverter PCB Design

Abstract

Automotive inverter PCBs have to carry both high-speed switching signals and large currents on the same layers, which makes the layout far more sensitive than it might first appear. A trace that is a few tenths of a millimeter too narrow, or a via that is not back-drilled, can show up later as excessive insertion loss, an EMI compliance failure, unexpected heating, or all of these together. This thesis examines how such layout decisions affect signal integrity, electromagnetic interference, DC resistance, and thermal performance, using a set of purpose-built test boards that were simulated and then measured in hardware to confirm the results. Rather than analyzing a full inverter PCB where every effect is tangled together, dedicated structures were designed to isolate specific mechanisms individually: via stubs, return-path discontinuities, crosstalk, current distribution, and power-plane resonance. The results tell a fairly consistent story: small layout details matter more than one might expect. Via stubs degrade signal transmission at high frequency, and back-drilling largely fixes it. A return-path split increases insertion loss above 1 GHz, but a 100 nF stitching capacitor recovers much of that loss. Widening trace spacing from 1W to 3W cut near-end crosstalk from 96.7 mV to 52.9 mV, though far-end crosstalk actually went up, since the wider-spacing structure also had a longer coupled section. On the DCIR side, going from one via to four dropped current density from 34.45 A/mm2 to 13.14 A/mm2, and widening a trace from 0.25 mm to 10 mm brought the voltage drop down from 584.5 mV to 26.4 mV, with a corresponding thermal improvement from roughly 182 °C down to 27 °C. In the EMI test board, the third harmonic of an 80 MHz signal excited a power-plane resonance around 240 MHz, and adding a second decoupling capacitor cut the measured near-field emission peak by about 17 dB. Taken together, the work shows that fairly modest changes to a PCB layout can shift electrical and thermal performance substantially, and it offers a simulation methodology, validated against hardware, for catching these effects before a board is built.