AXI4 Interfaces on a Deep Neural Network Accelerator

Abstract

The demand for artificial intelligence in intellectual property and hardware platforms including field-programmable gate arrays and application-specific integrated circuits is rapidly increasing, especially in fields such as computer vision, radar, and image analysis. However, traditional artificial intelligence acceleration methods are facing challenges due to the surge in data volumes, necessitating the development of sustainable computing solutions. Reconfigurable devices, renowned for their high customization, adaptability, and parallelism properties, are emerging as pivotal components in addressing these challenges.

This thesis project investigates the integration of an AMBA AXI4-Lite slave interface into a deep neural network accelerator intellectual property core using VHDL. The primary objective is to optimize communication channels between accelerators and processors, thereby enhancing system configuration accuracy and memory management efficiency. The anticipated outcome encompasses performance enhancements based on the implementation of the AXI4-Lite slave interface. The study extends its scope to include optimize communication pathways and exploring novel approaches to system configurations and memory management within the intellectual property core design.