Implementing an AC97Audio Controller IP

Abstract

The purpose of this Master’s project is to develop an AC97 IP core for Aeroflex Gaisler AB. The IP core’s function is to control the playback of digital audio in an embedded system and it will be introduced in a LEON3-based system, which is programmed in a Virtex 5 FPGA in the Xilinx ML505 prototype board. The core is implemented in VHDL using the Two Process Methodology. The design of the AC97 core was divided in two stages. The first stage of the design aimed to achieve communication among the LEON3-based system, the AC97 core, and the AC97 CODEC (controlled by the AC97 IP core); in the second stage of the design, a DMA engine was introduced to transfer PCM data from memory to the CODEC. Through the medium of assessing the thesis objectives and the obtained outcomes, the design of the AC97 IP core was partially verified. Simulation in ModelSim was carried out for both stages. The second stage of the design still has to be thoroughly verified in hardware by playing real audio on the Xilinx prototype board.