Evaluation of IGBT gate parasitics by means of a PEEC based tool

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/173817
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Type: Examensarbete för masterexamen
Master Thesis
Title: Evaluation of IGBT gate parasitics by means of a PEEC based tool
Authors: Madadi, Aryan
Abstract: In this thesis work, as a part of SEMikado project, a modeling platform is developed in BusBar Tool for studying the IGBT StakPak gate prints to be used in HVDC Light and SVC Light applications. Parasitic elements of two IGBT StakPak gate print designs have been extracted and the effects of several parameters including emitter plate, couplings and skin effect have been modeled and analyzed. SPICE models obtained from BusBar Tool simulations have been imported into PSpice and have been put into the desired test circuit in each simulation scenario to evaluate the IGBT positions. A PSpice circuital schematics test circuit has been built for studying the separated gate print which provides a better overview on parasitic elements. Two gate print designs have been compared through several simulation scenarios, regarding their parasitic elements, hence maximum voltage overshoots and time delays.
Keywords: Elkraftteknik;Electric power engineering
Issue Date: 2013
Publisher: Chalmers tekniska högskola / Institutionen för energi och miljö
Chalmers University of Technology / Department of Energy and Environment
URI: https://hdl.handle.net/20.500.12380/173817
Collection:Examensarbeten för masterexamen // Master Theses

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